PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 398

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 076BH: RXSDQ FIFO Indirect Cells and Packets Count
COUNT[3:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register is used to read the 4-bit FIFO counters for the enabled FIFOs, which count the
number of ATM cells or POS packets currently in the FIFO, modulo 4.
These read-only bits hold the last sampled count for the FIFO requested in the RXSDQ FIFO
Indirect Address register’s PHYID[5:0] bits. This register is latched when register 0000H is
written to for a global performance monitor update. After the count is latched into the
register, the internal counter is reset to 0 and starts counting again. When this counter reaches
its maximum count, it rolls over. This register must be accessed via an indirect register read
or write via register 0768H. See also section 13.19: Accessing Indirect Registers.
The counters provided by the RXSDQ are purely for diagnostic purposes. They should
be ignored in normal operation.
Type
R
R
R
R
Unused
Unused
Unused
Unused
Unused
Unused
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
Function
Unused
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
398