PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 540

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.18 Interrupt Service Routine
13.19 Accessing Indirect Registers
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Repeat steps 4 to 6 by writing the values 0x0006 and 0x000A into register 0x0720 to configure
the remaining STS-1 channels residing in timeslots 6 and 10 respectively.
Set RPAISINS_EN register bit to 1 in register 0x0902.
Note that an STS-12c channel residing in the first STS-12 position can also be configured using
the exact steps 1 to 3.
Note that the other features of the SARC such as Section TLRDIINS Enable, Path Configuration,
Path RALM Enable, LOP Pointer Status, LOP Pointer Interrupt Enable, LOP Pointer Interrupt
Status, AIS Pointer Status, AIS Pointer Interrupt Enable, and AIS Pointer Interrupt Status should
not be used for non-STS-48c modes.
Also note that PAIS will not be generated as a consequential action to Loss of Pointer LOP, Loss
of Concatenated Pointer LOPC, or Concatenated AIS detection PAISC.
The S/UNI-2488 will assert INTB to logic 0 when a condition which is configured to produce an
interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined
below should be followed:
1. Read the S/UNI-2488 Master Interrupt Status #1-#7 registers (0004H – 000AH). The bits
2. Find the register address of the corresponding block which caused the interrupt and read its
3. Service the interrupt(s).
4. If the INTB pin is still logic 0, then there are still interrupts to be serviced and steps 1 to 3
Indirect registers are used to conserve address space in the S/UNI-2488. Indirect registers are
accessed by writing the indirect address register. The following steps should be followed for
writing to indirect registers:
1. Read the BUSY bit. If it is equal to logic 0, continue to step 2. Otherwise, continue polling
2. Write the desired configurations for the channel into the indirect data register(s).
point to the functional block(s) which caused the hardware interrupt. For instance, if the
RXSDQ block caused the interrupt, the RXSDQI bit will be logic 1 in register 0008H. These
bits get cleared when the interrupt is cleared.
Interrupt Status registers. The interrupt functional block and interrupt source identification
register bits from steps 1 and 2 are cleared once these register has been read and the
interrupt(s) identified.
need to be repeated. Otherwise, all interrupts have been serviced. Wait for the next assertion
of INTB.
the BUSY bit.
S/UNI-2488 Telecom Standard Product Datasheet
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