PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 378

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0750H: TCFP Configuration
All Reserved bits must be set to their default values for proper operation.
PROV
SCRMBL
FLAG[3:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The processor provision bit (PROV) is used to enable the TCFP. When PROV is logic 0, the
TCFP ATM and packet processors are disabled and will not request data from the TXSDQ
FIFO interface and will respond to data requests with all 1’s data. When PROV is logic 1, the
TCFP ATM or packet processor is enabled and will respond to data requests with valid data
after requesting and processing data from the TXSDQ FIFO interface.
The SCRMBL bit controls the scrambling of the packet data stream or ATM cell payload.
When SCRMBL is a logic 1, scrambling is enabled. When SCRMBL is a logic 0, scrambling
is disabled.
The flag insertion control (FLAG[3:0]) configures the minimum number of flag bytes the
packet processor inserts between packets. The minimum number of flags (01111110) inserted
between packets is shown in the table below. FLAG[3:0] are used only in POS mode. This
register is to be a static value; it should not be modified during normal operation.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
FIFO_ERRE
FIFO_UDRE
XFERE
Reserved
Reserved
DELINDIS
Reserved
POS_SEL
CRC_SEL[1]
CRC_SEL[0]
FLAG[3]
FLAG[2]
FLAG[1]
FLAG[0]
SCRMBL
PROV
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
Released
378