PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 518

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Frequency offsets (e.g., due to plesiochronous network boundaries or the loss of a primary
reference-timing source) and phase differences (due to normal network operation) between the
incoming and the outgoing streams are accommodated by outgoing pointer adjustments.
Outgoing pointer justification events are indicated on two separate outputs. A slave SVCA uses
one of these outputs to perform the required justification when a concatenated STS-48c/STM-16c
is processed. The other set of outputs can be used for performance monitoring. Excessive pointer
justification events may indicate network synchronisation failure. Finally, the SVCA provides
pointer justification performance counters for each path.
The SVCA aligns the synchronous payload of any legal mix of STS-1/3c/12c (VC-3/4/4c). The
STS (VC) payloads are independently floating inside the STS-12 (STM-4) transport frame. The
SVCA aligns each one independently. The output pointer justification events are multiplexed
among all the output streams.
Each SVCA provides an interrupt output to indicate any changes in the status of output pointer
justification (NJE, PJE) and FIFO overflows or underflows. Each interrupt source is
independently maskable.
The SVCA modifies the transport overhead as follows (Table 25 shows the STS-1 configuration):
Table 25 SVCA STS-1 Transport Overhead Modification
In the cross connect mode of operation, the APSMUX_RCFP and APSMUX_T8TE register bits
must be set to logic 1 so that data are output on the APSO_P/ APSO_N[4:1] port as well as
received on the APSI_P/ APSI_N[4:1] port in the correct manner. Please see the S/UNI-2488
Master Reset, Configuration and Loopback register (register 0001H) for a complete description.
For proper operation in a CHESS system, the T8TEs' CENTER bit must be set to logic 1 after the
APS CSU is locked. This is the only way to guarantee that all transmit FIFO depths are within 1
or 2 clock cycles of each other. This is required for J0 alignment at the far end.
When XCONNECTMODE is a logic 1, the behavior of the POS-PHY Level 3 / UTOPIA Level
3™ port is undefined, since that port is only configured to operate as a single port device.
Section
Overhead
Pointers
Line Overhead
A1
00
00
H1
00h
00h
00h
00h
00h
A2
00
00
H2
00h
00h
00h
00h
00h
00
00
H3 : Negative Opportunity
00h
00h
00h
00h
00h
00
S/UNI-2488 Telecom Standard Product Datasheet
P0 : Positive Opportunity
Released
518