PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 386

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TX_BYTE_MODE
DCRC[7:0]
The transmit byte counter mode (TX_BYTE_MODE) bit is used to select the mode in which
the TX_BYTE[39:0] counters work. When TX_BYTE_MODE is logic 0, TX_BYTE[39:0]
will count all bytes in transmitted packets (including FCS and Abort bytes) before the byte
stuffing operation. When TX_BYTE_MODE is logic 1, TX_BYTE[39:0] will count all bytes
in transmitted packets (including FCS, Abort, and stuff bytes) after the byte stuffing
operation. Flag bytes will not be counted in either case. The TX_BYTE_MODE bit is only
valid when working in POS mode.
The diagnostic CRC word (DCRC[7:0]) configures the ATM or packet processor to logically
invert bits in the inserted CRC on the outgoing data stream for diagnostic purposes. When
any bit in DCRC[7:0] is set to logic 1, the corresponding bit in the FCS value inserted by the
POS processor or the HCS value inserted by the ATM processor is logically inverted.
DCRC[7:0] is ignored when no FCS is inserted. Each DCRC[x] bit will cause a bit error in
each byte of the 2 byte or 4 byte FCS.
S/UNI-2488 Telecom Standard Product Datasheet
Released
386