PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 371
PM5381-BI
Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5381-BI.pdf
(586 pages)
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
CLP
PTI[2:0]
GFC[3:0]
The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet
cell, in conjunction with the Idle Cell Header and Mask register bit. The IDLEPASS bit in
the RCFP Configuration Register must be set to logic 0 to enable dropping of cells matching
this pattern.
The PTI[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth
octet of the 53-octet cell, in conjunction with the Idle Cell Header and Mask register bits.
The IDLEPASS bit in the RCFP Configuration Register must be set to logic 0 to enable
dropping of cells matching this pattern.
The GFC[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of
the first octet of the 53-octet cell, in conjunction with the Idle Cell Header and Mask register
bits. The IDLEPASS bit in the RCFP Configuration Register must be set to logic 0 to enable
dropping of cells matching this pattern.
Note that an all-zeros pattern must be present in the VPI and VCI fields of the Idle or
unassigned cell.
S/UNI-2488 Telecom Standard Product Datasheet
Released
371
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