PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 573

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
2.
3.
4.
5.
6.
7.
Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface
data bus, (D[15:0]).
A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
tV
Parameter tH
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
l
, tS
lr
, and tH
ar
lr
is not applicable if address latching is used.
are not applicable.
S/UNI-2488 Telecom Standard Product Datasheet
alr
Released
, tH
573
alr
,