PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 481

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0885H: TXDLL Vernier Control
The Vernier Control Register provides the delay line tap control when using the vernier option.
VERNIER[7:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The vernier tap register bits (VERNIER[7:0]) specifies the phase delay through the DLL
when using the vernier feature. When VERN_EN is set high, the VERNIER[7:0] registers
specify the delay tap used. When VERN_EN is set low, the VERNIER[7:0] register is
ignored.
A VERNIER[7:0] value of all zeros specifies the delay tap with the minimum delay through
the delay line. A VERNIER[7:0] value of 255 specifies the delay tap with the maximum
delay through the delay line.
This bit must be set to logic 0 for normal operation.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
Unused
Unused
VERNIER[7]
VERNIER[6]
VERNIER[5]
VERNIER[4]
VERNIER[3]
VERNIER[2]
VERNIER[1]
VERNIER[0]
Function
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
0
0
0
0
0
Released
481