PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 290

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 00H: THPP Control Register
All Reserved bits must be set to their default values for proper operation.
PREIEBLK
FSBEN
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The path REI block error (PREIEBLK) bit controls the extraction of path REI errors in the
PREI monitoring block of the STS/AU pointer. When PREIEBLK is set to logic 1, the path
REI extracted represents BIP-8 block errors (a maximum of 1 error per frame). When
PREIEBLK is set to logic 0, the path REI extracted represents BIP-8 errors (a maximum of 8
errors per frame).
This bit is only valid for THPP STS-1/STM0 #1.
When the FSBEN register bit is logic one, THPP overwrites the fixed stuff byte. The value
used is that programmed in the FSB field of THPP Indirect Register 04H. Note that if the
channel is unequipped, this bit may be set and the value changed to whatever value is being
transmitted in the unequipped payload. This bit has no effect when TPAIS_EN is set high and
Path AIS is being transmitted.
This bit is valid for and should be consistent for the first four STS-1 timeslots of each THPP
as these are the only FSB bytes in an STS-48c.
Type
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Unused
FSBEN
PREIEBLK
Reserved
Unused
Default
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
290