PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 385

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0753H: TCFP Diagnostics
All Reserved bits must be set to their default values for proper operation.
INVERT
XOFF
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The data inversion bit (INVERT) configures the ATM or packet processor to logically invert
the outgoing data stream. When INVERT is set to logic 1, the outgoing data stream is
logically inverted. The outgoing data stream is not inverted when INVERT is set to logic 0.
The XOFF serves as a transmission enable bit. When XOFF is set to logic 0, ATM cells or
packets are transmitted normally. When XOFF is set to logic 1, the cell or packet currently
being transmitted is completed and then transmission is suspended. When XOFF is set to
logic 1, the TCFP will request data from the FIFO until its own internal FIFO is full
(maximum 56 bytes). ATM Idle cells or HDLC flags will be sent on the TCFP egress
interface.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
DCRC[7]
DCRC[6]
DCRC[5]
DCRC[4]
DCRC[3]
DCRC[2]
DCRC[1]
DCRC[0]
Reserved
Reserved
TX_BYTE_MODE
XOFF
INVERT
Reserved
Reserved
Reserved
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Released
385