PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 196

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
F1REGEN
D1D3REGEN
K1K2REGEN
D4D12REGEN
S1REGEN
Z1REGEN
The F1 register enable (F1REGEN) bit controls the insertion of section user channel in the
data stream. When F1REGEN is set to logic 1, the section user channel from the TRMP
Transmit E1 and F1 register is inserted in the F1 byte of STS-1/STM-0 #1 according to the
priority of Table 4. When F1REGEN is set to logic 0, the section user channel from the
TRMP Transmit E1 and F1 register is not inserted.
The D1 to D3 register enable (D1D3REGEN) bit controls the insertion of section data
communication channel in the data stream. When D1D3REGEN is set to logic 1, the section
DCC from the TRMP Transmit D1D3 and D4D12 register is inserted in the D1 to D3 bytes of
STS-1/STM-0 #1 according to the priority of Table 4. When D1D3REGEN is set to logic 0,
the section DCC from the TRMP Transmit D1D3 and D4D12 register is not inserted.
The K1K2 register enable (K1K2REGEN) bit controls the insertion of automatic protection
switching in the data stream. When K1K2REGEN is set to logic 1, the APS bytes from the
TRMP Transmit K1 and K2 register are inserted in the K1, K2 bytes of STS-1/STM-0 #1
according to the priority of Table 4. When K1K2REGEN is set to logic 0, the APS bytes
from the TRMP Transmit K1 and K2 register are not inserted.
The D4 to D12 register enable (D4D12REGEN) bit controls the insertion of line data
communication channel in the data stream. When D4D12REGEN is set to logic 1, the line
DCC from the TRMP Transmit D1D3 and D4D12 register is inserted in the D4 to D12 bytes
of STS-1/STM-0 #1 according to the priority of Table 4. When D4D12REGEN is set to logic
0, the line DCC from the TRMP Transmit D1D3 and D4D12 register is not inserted.
The S1 register enable (S1REGEN) bit controls the insertion of the synchronization status
message in the data stream. When S1REGEN is set to logic 1, the SSM from the TRMP
Transmit S1 and Z1 register is inserted in the S1 byte of STS-1/STM-0 #1 according to the
priority of Table 4. When S1REGEN is set to logic 0, the SSM from the TRMP Transmit S1
and Z1 register is not inserted.
The Z1 register enable (Z1REGEN) bit controls the insertion of Z1 growth bytes in the data
stream. When Z1REGEN is set to logic 1, the Z1 byte from the TRMP Transmit S1 and Z1
register is inserted in the Z1 bytes according to the priority of Table 4. When Z1REGEN is
set to logic 0, the Z1 byte from the TRMP Transmit S1 and Z1 register is not inserted.
S/UNI-2488 Telecom Standard Product Datasheet
Released
196