PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 521

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
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In the transmit direction, the S/UNI-2488 calculates the B2 values. The calculated code is then
placed in the next frame.
In the receive direction, the S/UNI-2488 calculates the B2 code over the current frame and
compares this calculation with the B2 code receive in the following frame. Receive B2 errors are
accumulated in an error event counter.
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In the transmit direction, the S/UNI-2488 provides register control for the K1 and K2 bytes.
In the receive direction, the S/UNI-2488 provides register access to the filtered APS channel.
Protection switch byte failure alarm detection is provided. The K2 byte is examined to determine
the presence of the line AIS, or the line RDI maintenance signals
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In the transmit direction, the S/UNI-2488 provides register control for the synchronization status
byte.
In the receive direction, the S/UNI-2488 provides register access to the synchronization status
byte.
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In the transmit direction, Z2 byte is internally generated. The number of B2 errors detected in the
previous interval is inserted.
In the receive direction, a legal Z2 byte value is added to the line FEBE event counter.
B2: The line bit interleaved parity bytes provide a line error monitoring function.
K1, K2: The K1 and K2 bytes provide the automatic protection switching channel. The K2
byte is also used to identify line layer maintenance signals. Line RDI is indicated when bits
6, 7, and 8 of the K2 byte are set to the pattern '110'. Line AIS is indicated when bits 6, 7,
and 8 of the K2 byte are set to the pattern '111'.
D4 - D12: The line data communications channel provides a 576 kbit/s data communications
channel for network element to network element communications.
S1: The S1 byte provides the synchronization status byte. Bits 5 through 8 of the
synchronization status byte identifies the synchronization source of STS-48c (STM-16c)
signal. Bits 1 through 4 are currently undefined.
Z1: The Z1 bytes are located in the second and third STS-1’s locations of an STS-48c (STM-
16c) and are allocated for future growth.
M1: The M1 byte is located in the third STS-1 location of a STS-48c (STM-16c) and
provides a line far end block error function for remote performance monitoring.
Z2: The Z2 bytes are located in the first and second STS-1’s locations of a STS-12c (STM-
4c) and are allocated for future growth.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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