PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 166

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
SLLE
TX2488_MODE[2:0]
The serial line loop-back enable (SLLE) bit loops the recovered data and clock to the transmit
output. When this bit is set to logic 1, data from the 2488 receiver is input into the PISO and
data from the SONET transmit processor is ignored.
Note: The CSU_MODE[7] bit of the CSU Control register must be set to logic 0 when SLLE
is enabled.
For chip-level line loopback, the LINE_LOOP_BACK bit in the Rx2488 Analog CRU Clock
Training Configuration and Status register (register 0013H) and the SLLE register bit in the
Tx2488 Analog Control/Status register (register 0020H) must be set to logic 1. As well, the
CSU_MODE[7] register bit in the Tx2488 ABC Control register (register 0021H) must be set
to logic 0.
The TX2488 Mode control bits are used to place the TX2488-CML in one of the following
operating modes:
Table 10 TX2488 Mode Control
TX2488_MODE [2:0]
Value
111
1XX
0XX
X11
X10
X01
X00
Description
Reserved
Reserved
When MODE[2] is set low, the data from PISO-2488 is used as the input
to the transmitter. The default is to use the PISO-2488 as the input.
Reserved
Reserved
When the configuration bits MODE0 and MODE1 are set respectively high
and low, limited-swing AC coupling suitable for the Lucent T48, Hitachi
HTR6540, or HP HFCT-53D5 ODL transmitters is used. In this mode a
16mA bias current is generated in the differential CML transmitter that is
based on an internal reference resistor matched with the output stage
load. The generated current produces a differential amplitude suitable for
the Lucent T48, Hitachi HTR6540 or HP HFCT-53D5 (using double
termination).
When the configuration bits MODE1 and MODE0 are set low, AC coupling
suitable for PECL compliant ODL transmitters (e.g. Sumitomo SDM7128-
XC or Sumitomo SCM6028-GL) is used. In this mode a 30.5mA bias
current is generated in the differential CML transmitter that is based on an
internal reference resistor matched with the output stage load. The
generated current is adequate to produce a valid differential PECL
amplitude with double termination.
S/UNI-2488 Telecom Standard Product Datasheet
Released
166