PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 310

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0608H, 0628H, 0648H, 0668H: SVCA FIFO Interrupt Enable
In the XCONNECT mode of operation of the S/UNI-2488, the FIEN[12:1] register bits are
defined as follows:
FIEN[12:1]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The FIFO event interrupt enable (ESEEN[12:1]) bits control the activation of the interrupt
(INT) output for STS-1/STM-0 paths #1 to #12 caused by a FIFO overflow or a FIFO
underflow. When any of these bit locations is set to logic 1, the corresponding pending
interrupt will assert the interrupt (INT) output. When any of these bit locations is set to logic
0, the corresponding pending interrupt will not assert the interrupt (INT) output. If
WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set
to logic 0, then a read of this register automatically clears this bit.
In the normal mode of operation of the S/UNI-2488 only the first register address (0608H) is
used. The FIEN[12:2] register bits are unused in normal mode and the FIEN[1] register bit is
defined as follows:
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
FIEN[12]
FIEN[11]
FIEN[10]
FIEN[9]
FIEN[8]
FIEN[7]
FIEN[6]
FIEN[5]
FIEN[4]
FIEN[3]
FIEN[2]
FIEN[1]
Default
0
0
0
0
0
0
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
310