PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 464

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
LLBEN
TPINS
FIFOERRE
Reserved
The FIFO should be CENTERed whenever any of the following actions are taken: (1) the
chip is reset/powered on, (2) CSU is reset, (3) APS is reset or (4) the position of APSIFP
changes.
For proper operation in a CHESS system, the T8TEs' CENTER bit must be set to logic 1 after
the APS CSU is locked. This is the only way to guarantee that all transmit FIFO depths are
within 1 or 2 clock cycles of each other. This is required for J0 alignment at the far end.
The line loopback enable bit (LLBEN) controls line loopback operation. LLBEN routes the
raw 8b10b encoded receive stream from the LVDS receiver to the LVDS transmitter. There it
is serialized and transmitted without further processing. When LLBEN is set high, serial line
loopback is enabled. When LLBEN is set low, line loopback is disabled.
The Test Pattern Insertion (TPINS) controls the insertion of test pattern in the outgoing data
stream for jitter testing purpose. When this bit is set high, the test pattern stored in the
registers (TP[9:0]) is used to replace all the overhead and payload bytes of the output data
stream. When TPINS is set low, no test patterns are generated.
The FIFO overrun/underrun error interrupt enable bit (FIFOERRE) controls the FIFO overrun
interrupt event. An interrupt is generated on a FIFO error event if the FIFOERRE is set to
logic 1. No interrupt is generated if FIFOERRE if is set to logic 0.
Reserved should be kept at its default value.
S/UNI-2488 Telecom Standard Product Datasheet
Released
464