PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 159

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
OUTDATA
OUTLOCK
TRAIN
ROOLV
The clock difference detector DROPPING OUT OF DATA transition configuration bit
determines the number of times the clock difference detector must fail before the CRU
control state machine transitions from the DATA IN RANGE state to the LOCKED TO
REFERENCE state. When OUTDATA is a logic zero, the clock difference detector must fail
once before the state transition can take place. When OUTDATA is a logic one, the clock
difference detector must fail 39 consecutive times before the state transition can occur.
Note: This bit is recommended to be set to ‘1’ for robust operation of the CRU/state machine
in a noisy environment.
The clock difference detector DROPPING OUT OF LOCK transition configuration bit
determines the number of times the clock difference detector must pass before the CRU
control state machine transitions from the LOCKED TO DATA state to the DATA IN RANGE
state. When OUTLOCK is a logic zero, the clock difference detector must fail once before
the state transition can occur. When OUTLOCK is a logic one, the clock difference detector
must fail 39 consecutive times before the state transition can occur.
Note: This bit is recommended to be set to ‘1’ for robust operation of the CRU/state machine
in a noisy environment.
The CRU reference training status indicates if the CRU is locking to the reference clock or
the locking to the receive data. TRAIN is a logic zero if the CRU is locking or locked to the
reference clock. TRAIN is a logic one if the CRU is locking or locked to the receive data.
TRAIN is invalid if the CRU is not used.
When the optical signal is lost, the SD input pin is expected to be deasserted. In this state, the
CRU will be forced into training mode and will lock to REFCLK. However, the state-
machine which controls the TRAIN register bit will continue looking at the data and will
occasionally change states. However, the CRU will remain locked to REFCLK until SD is
once again asserted.
The recovered reference out of lock status indicates that the clock recovery phase locked loop
is unable to lock to the reference clock on REFCLK. At startup, ROOLV may remain at logic
1 for several hundred milliseconds while the PLL obtains lock.
S/UNI-2488 Telecom Standard Product Datasheet
Released
159