PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 174

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0038H: STLI Clock Configuration
Reserved1 This register bit must be set to logic 1 for normal operation.
TCLKEN
Reserved
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The transmit clock enable (TCLKEN) bit controls the gating of the TCLK output clock.
When TCLKEN is set to logic 1, the TCLK output operates normally. When TCLKEN is set
to logic 0, the TCLK output is held low.
The Reserved bits must be left in their default values for proper operation.
Type
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
TCLKEN
Reserved1
S/UNI-2488 Telecom Standard Product Datasheet
Default
1
0
0
0
0
0
Released
174