PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 529

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

13.12.1 TPAHOLD = 0
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TDAT[31:0]
TMOD[1:0]
TPRTY
TFCLK
TSOP
TEOP
TERR
TENB
DTPA
Figure 29 shows the behavior of DTPA when the TPAHOLD register bit (in register 788H
TXPHY Configuration) is set to logic 0. This is the default operating mode. In this example,
the write to the FIFO which occurs at the start of cycle 7 crosses the TXSDQ’s BT[4:0] threshold.
DTPA responds on cycle 12. There is a 5 clock cycle delay between the write and the response on
DTPA.
Figure 29 TPAHOLD Set To 0
This 5 cycle delay can be dealt with in 2 ways. First, the upstream device can be programmed to
wait for the response before sampling the new DTPA status. For small transfers, this may affect
the net throughput possible on the PL3 bus. For this case, the TXSDQ buffer threshold can be set
equal or greater than the PL3 burst-size of the upstream device.
BT[4:0] ³ burst-size – 1
Where burst-size is in units of blocks (1 block = 16 bytes).
Second, if the upstream device cannot account for the DTPA delay or maximum throughput is
desired on the PL3 bus, the TXSDQ’s buffer threshold must be set to guarantee that any transfers
which occur during the 5 cycle delay do not cause any overflows. To do this, the value of the
TXSDQ’s buffer threshold may need to be increased. It can be calculated by using the following
equation:
Where:
1
1000
BT[4:0] ³ 1 + (num_min_pack * min_pack_size_in_blocks) + remainder - 1
Let m = minimum packet size
Let s = upstream device's response time to DTPA (# of clocks after DTPA
B1-B4
2
for transfer to stop)
3
4
5
1000
6
B1-B4
B5-B8
7
S/UNI-2488 Telecom Standard Product Datasheet
B9-B12
8
B13-B16
9
B17-B20
10
B21-B24
11
B25-B28
12
Released
529