PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 369

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0745H: RCFP LCD Count Threshold
LCDC[10:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The LCDC[10:0] bits represent the number of consecutive cell periods the receive cell
processor must be out of cell delineation before loss of cell delineation (LCD) is declared.
Likewise, LCD is not deasserted until the receive cell processor is in cell delineation for the
number of cell periods specified by LCDC[10:0].
The default value of LCD[10:0] is 360. For STS-48c, the average cell period is 176.9 ns and
the default LCD integrate period is 63.8 ms.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
LCDC[10]
LCDC[9]
LCDC[8]
LCDC[7]
LCDC[6]
LCDC[5]
LCDC[4]
LCDC[3]
LCDC[2]
LCDC[1]
LCDC[0]
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
0
0
1
0
1
1
0
1
0
0
0
Released
369