PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 553

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

14.3
14.3.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
APSO_P[X]/APSO_N[X]
APSO_P[Y]/APSO_N[Y]
Figure 38 Outgoing APS Serial TelecomBus Timing
ATM UTOPIA Level 3™ System Interface
The ATM UTOPIA Level 3 System Interface is compatible with the UTOPIA Level 3
specification. The S/UNI-2488 only supports the 32-bit mode of operation.
Transmit UL3 Interface
The Transmit UTOPIA Level 3 System Interface Timing diagram (Figure 39) illustrates the
operation of the system side transmit UL3 interface. The single PHY case shown in Figure 39
illustrates the behavior of the TCA signal. At the start of cycle 4, there is only enough FIFO
buffer space for the cell being transferred so TCA is deasserted. The deassertion occurs on the
TFCLK edge after TSOC of the cell (cell#1) being written to the FIFO is sampled. This cell will
take the last remaining cell buffer space in the FIFO. This TCA behavior is consistent with the
Utopia L3 specification which states that TCA is invalid on the TFCLK edge that initiates the
transition of TSOC to logic 1.
On cycle 5, a cell has been read out of the FIFO to the S/UNI-2488 core so it now has room to
accommodate the cell currently being transferred (cell#1) plus one additional cell (cell#2). At
the start of cycle 8, the transfer of cell#1 is completed. TCA remains high because there is still
buffer space for one more cell. At the start of cycle 10, transfer of cell#2 starts. TCA is
deasserted at cycle 11 because besides the space for holding cell#2, there is no FIFO space for
any more cells.
If TENB is held low, back-to-back cell transfers can be performed without a dead cycle.
TSOC must be high during the first byte of the ATM cell structure and must be present for the
start of each cell. Thus, TSOC will mark the H1 byte. If TSOC is asserted at the wrong time
(not at proper cell boundaries), a corrupted (but complete) cell will be transmitted from the
S/UNI-2488. This corrupted cell will contain the bytes from the runt cell transferred through the
UL3 interface plus some random bytes to fill the remainder of the ATM cell.
APSIFPCLK
APSOFP
APSIFP
1
2
3
4
S/UNI-2488 Telecom Standard Product Datasheet
5
A2
A2
approx. 22 APSIFPCLK cycles
approx. 22 APSIFPCLK cycles
6
J0
J0
7
Z0
Z0
8
Z0
Z0
9
Z0
Z0
10
Z0
Released
Z0
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