PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 49

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
When used to implement a Packet over SONET/SDH link, the S/UNI-2488 inserts POS frames
into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a
192x16-byte FIFO (programmable FIFO depth – all packets are 16 byte block aligned) through a
32-bit SATURN POS-PHY Level 3™ (clocked up to 104 MHz) system side interface. POS
frames are built by inserting the flags, control escape characters and the FCS fields. Either the
CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided
for performance monitoring.
No line rate clocks are required directly by the S/UNI-2488 as it synthesizes the transmit clock
and recovers the receive clock using a 155.52 MHz reference clock. The S/UNI-2488 outputs a
differential PECL line data (TXD_P/ TXD_N).The S/UNI-2488 is configured, controlled and
monitored via a generic 16-bit microprocessor bus interface. The S/UNI-2488 also provides a
standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI-2488 is implemented in low power, +1.8 Volt, CMOS technology. It has
LVTTL/CMOS compatible digital inputs and LVTTL/CMOS compatible digital outputs. High
speed inputs and outputs support 3.3V compatible pseudo-ECL (PECL). The S/UNI-2488 is
packaged in a 416 pin UBGA package.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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