PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 554

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

14.3.2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
TDAT[31:0]
TPRTY
TFCLK
TSOC
TENB
TCA
Figure 39 Transmit UTOPIA Level 3 System Interface Timing for Single PHY
Receive UL3 Interface
The Receive UTOPIA Level 3 System Interface Timing diagrams (Figure 40) illustrate the
operation of the system side receive interface.
The single PHY case shown in Figure 40 illustrates the behavior of the RCA signal. At the start
of cycle 3, RENB is sampled low which initiates a cell transfer from the S/UNI-2488. The
transfer begins at cycle 4. The response to RENB always occurs on the rising RFCLK edge
following the RFCLK edge which samples RENB. Also note that RENB must remain asserted
during a cell transfer as specified by the Utopia L3 standard. In Figure 40, this occurs on the
rising edge of RFCLK at the start of cycle 9.
RCA is deasserted in cycle 4 and 11 coincident with the RSOC assertion indicating that the cell
transfer which has just started contains the last cell in the FIFO at this time. RCA may be
asserted at any time due to the insertion of a complete cell into the FIFO.
Back-to-back cells from the same PHY can be handled by holding RENB asserted at logic 0
during cycle 8. In this case, cycle 10 for RSOC, RDAT[31:0], and RPRTY will be eliminated and
the following cycles will be advanced.
1
2
H1
3
P1
4
P2
5
P3
6
S/UNI-2488 Telecom Standard Product Datasheet
7
P12
8
9
H1
10
P1
11
P2
Released
P3
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