PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 75

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

10.1
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Functional Description
Receive Line Interface
The Receive Line Interface allows direct interface of the S/UNI-2488 to optical modules (ODLs)
or other medium interfaces. This block performs clock and data recovery on the incoming
2488.32 Mbit/s data stream and SONET A1/A2 pattern framing.
The clock recovery unit recovers the clock from the incoming bit serial data stream and is
compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a
low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal
conditions, the clock recovery unit continues to output a line rate clock that is locked to this
reference for keep-alive purposes. The clock recovery unit utilizes a 155.52 MHz reference
clock. The clock recovery unit provides status bits that indicate whether it is locked to data or the
reference and also supports diagnostic loopback and a loss of signal input that squelches normal
input data.
Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of
the recovered clock is close enough to that of the reference clock (approx. +/-488 ppm), the PLL
attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data
transitions occur in 128 bit
reference clock. In order to avoid bit error due to lack of edges, a transition density of
approximately 50% over 1 second is required. This is generally assured when using SONET
scrambling.
When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the
transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal
condition. To meet the Bellcore GR-253-CORE SONET Network Element free-run accuracy
specification, the reference must be within ±4.6 ppm. When not loop timed, the REFCLK
accuracy may be relaxed to ±20 ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received SONET data signal. The total loop dynamics
of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance specified
for SONET equipment by GR-253-CORE. Please refer to the figure below.
1
This number is programmable through LOS_COUNT[4:0] in Register 0013H.
1
bit periods or if the recovered clock drifts beyond 1000 ppm of the
S/UNI-2488 Telecom Standard Product Datasheet
Released
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