Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 10

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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UM008101-0601
Z80 CPU Peripherals
User Manual
Direct Memory Access (continued)
Figure 24. Variable Cycle Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 25. Pin Functions (CMOS PLCC Package Only) . . . . . . . . . . 67
Figure 26. 40-Pin DIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 27. 44-Pin PLCC Pin Assignments (Z8410 NMOS) . . . . . . . . 69
Figure 28. 44-Pin PLCC Pin Assignments (Z84C10 NMOS) . . . . . . 70
Figure 29. Z80 DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 30. Write Register Organization (left) and Read Register Organi-
Figure 31. Bus-Requesting Daisy-Chain . . . . . . . . . . . . . . . . . . . . . . 79
Figure 32. Z80 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 33. Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 34. Interrupt Pending (IP) Latch . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 35. Interrupt Under Service (IUS) Latch . . . . . . . . . . . . . . . . . 84
Figure 36. Interrupt On Ready (IOR) Latch . . . . . . . . . . . . . . . . . . . . 86
Figure 37. Interrupt Daisy-Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 38. Polling for a Service Request Bit . . . . . . . . . . . . . . . . . . . 89
Figure 39. Write-Register Pointing Methods . . . . . . . . . . . . . . . . . . . 92
Figure 40. Write Register 0 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 41. Write Register 1 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 42. Write Register 2 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 43. Write Register 3 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 44. Write Register 4 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 45. Write Register 5 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 46. Write Register 6 Group . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 47. Read Register 0 through Read Register 6 . . . . . . . . . . . . 116
Figure 48. Z80/Z8000 Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 49. Chip Enable Decoding with Z80 CPU . . . . . . . . . . . . . . 131
zation (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
List of Figures