Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 278
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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Table 8. Contents of Write Registers 3, 4, and 5 in SDLC Modes
UM008101-0601
WR
3
WR
4
WR
5
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Bit 7
00 = Rx 5 Bits Char
10 = Rx 6 Bits Char
01 = Rx 7 Bits Char
11 = Rx 8 Bits Char
0
DTR
Bit 6
0
00 = Tx 5 Bits (or less)
Char
10 = Tx 6 Bits Char
01 = Tx 7 Bits Char
11 = Tx 8 Bits Char
information field may be sent to the Z80 SIO using the Transmit Interrupt
mode. The Z80 SIO transmits the Frame Check sequence using the
Transmit Underrun feature.
When the transmitter is first enabled, it is already empty and cannot then
become empty. Therefore, no Transmit Buffer Empty interrupts can occur
until after the first data character is written.
Data Transfer Using WAIT/READY
When the Wait/Ready function is selected, WAIT communicates to the
CPU that the Z80 SIO is not ready to accept the data and that the CPU must
extend the I/O cycle. To a DMA controller, READY communicates that the
transmitter buffer is empty and that the Z80 SIO is ready to accept the next
character. If the data character is not loaded to the Z80 SIO by the time the
transmit shift register is empty, the Z80 SIO enters the Transmit Underrun
condition. Address, control, and information fields may be transferred to
Bit 5
Auto
Enables
1
Selects
SDLC
Mode
Bit 4
Enter Hunt
Mode (if
incoming
data not
needed)
0
Selects
SDLC
Mode
0
Bit 3
Rx CRC
Enable
0
Tx Enable 0
Bit 2
Address
Search
Mode
0
Selects
SDLC
CRC
Bit 1
0
0
RTS
Serial Input/Output
Bit 0
Rx
Enable
0
Tx CRC
Enable
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