Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 270

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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tions are detected. The mode is reinitialized with the Enable Interrupt On
Next Receive Character command to allow the next character received to
generate an interrupt. Parity errors do not cause interrupts in this mode, but
End-of-Frame (SDLC mode) and Receive Overrun do.
If External/Status interrupts are enabled, they may interrupt any time DCD
changes state.
Interrupt On Every Character
Whenever a character enters the receive buffer, an interrupt is generated.
Error and Special Receive conditions generate a special vector if Status
Affects Vector is selected. Optionally, a Parity Error may be directed not to
generate the special interrupt vector.
Special Receive Condition Interrupts
The Special Receive Condition interrupt can occur only if either the
Receive Interrupt On First Character Only or Interrupt On Every Receive
Character modes is also set. The Special Receive Condition interrupt is
caused by the Receive Overrun error condition. Since the Receive Overrun
and Parity error status bits are latched, the error status-when read-reflects
an error in the current word in the receive buffer in addition to any Parity or
Overrun errors received after the last Error Reset command. These status
bits can only be reset by the Error reset command.
CRC Error Checking and Termination
A CRC error check on the receive message can be performed on a per char-
acter basis under program control. The Receive CRC Enable bit (WR3, D3)
must be set/reset by the program before the next character is transferred
from the receive shift register to the receive buffer register. This ensures
proper inclusion or exclusion of data characters in the CRC check.
To allow the CPU ample time to enable or disable the CRC check on a
particular character, the Z80 SIO calculates CRC eight bit times after the
character has been transferred to the receive buffer. If CRC is enabled
Serial Input/Output