Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 317

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Read Register 1
This register contains the Special Receive condition status bits and Residue
codes for the I-Field in the SDLC Receive Mode.
Table 32. Read Register 1 Special Receive Condition Status
All Sent (D0)
In asynchronous modes, this bit is set when all the characters have
completely cleared the transmitter. Transitions of this bit do not cause inter-
rupts and it is always set in synchronous modes.
Residue Codes 0, 1, and 2 (D3-D1)
In SDLC receive mode, these three bits indicate the length of the I-field,
when the I-field is not an integral multiple of the character length. These
codes are only meaningful for a transfer in which the End-of-Frame bit is
set (SDLC). For a receive character length of eight bits per character, the
codes signify the following:
Table 33. Residue Codes
Residue Code
(SDLC)
End of
Frame
D7
2
1
0
1
0
1
Framing
CRC/
Error
D6
Residue Code
Receiver
Overrun
Error
1
0
1
1
0
0
DS
Parity
Error
Residue Code
D4
0
0
0
0
1
1
Residue
Code 2
D3
I-Field Bits in
Previous Byte
Residue
Code 1
Z80 CPU Peripherals
D2
0
0
0
0
0
Serial Input/Output
Residue
Code 0
User Manual
D1
I-Field Bits in
Previous Byte
Second
All sent
3
4
5
6
7
D0
297