Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 126

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
the routine is being executed. Near the end of the routine, the CPU writes
an ENABLE INTERRUPTS command to the DIVA, which enables it to
generate a new interrupt.
This command is less extensive than the RESET AND DISABLE INTER-
RUPTS command because it does not reset the Interrupt Pending (IP) and
Interrupt Under Service (IUS) latches.
Figure 46.
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
Write Register 6 Group
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0 0
0 1
1 0
1 1
0 0
1 1
1 0
0 0
0 1
1 1
1 0
0 1
0 0
0 1
0 0
1 0
= C3 = Reset
= C7 = Reset Port A Timing
= C8 = Reset Port B Timing
= CF = Load
= D3 = Continue
= AF = Disable Interrupts
= AB = Enable Interrupts
= A3 = Reset and Disable Interrupts
= B7 = Enable after RETI
= BF = Read Status Byte
= 8B = Reinitialize Status Byte
= A7 = Initialize Read Sequence
= B3 = Force Ready
= 87 = Enable DMA
= 83 = Disable DMA
= BB = Read Mask Follows
1
Hex Command Name
1
Base Register Byte
Read Mask (1=Enable)
Status Byte
Byte Counter (Low Byte)
Byte Counter (High Byte)
Port A Address (Low Byte)
Port A Address (High Byte)
Port B Address (Low Byte)
Port B Address (High Byte)
Direct Memory Access