Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 107

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
are allowed in which the higher priority peripheral suspends the execution
of the lower priority peripheral’s service routine.
Bus-requesting daisy-chains do not have this preemption or nesting
ability. Instead, any peripheral that is able to get the bus keeps it until task
completion.
Figure 37.
Polling for Service Requests
When the CPU cannot detect interrupts directly, it polls an external gate as
shown in Figure 38.
Polling is accomplished in the following way:
•
•
CPU
Z80
Enable the DMA’s interrupt structure with a control byte
Poll a status bit to see when an interrupt request occurs
DMA
INT
+5V
INT
Interrupt Daisy-Chain
tristate enable line, normally at tristate,
for example, connected to a chip select decoder.
IEI
Interrupting Device
Highest Priority
INT
IEO
CPU
Pending
Polling
IEI
<   % 2 7 2 G T K R J G T C N U
INT
Direct Memory Access
IEO
7 U G T / C P W C N
To
Lower
Priority
Interrupting
Device