Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 288

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 10. SDLC Receive Mode
UM008101-0601
Function
Initialize WR0
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Register Information loaded:
WR0
WR2
WR0
SDLC Receive Termination
If enabled, a special vector is generated when the closing flag is received.
This signals that the byte with the End-of-Frame bit set has been received.
In addition to the results of the CRC check, RR1 has three bits of Residue
code valid at this time. When the number of bits in the I-Field is not an inte-
gral multiple of the character length used, these bits indicate the boundary
between the CRC check bits and the I-Field bits. For a detailed description
of the meaning of these bits, see the description of the residue codes in RR1
in “Z80 SIO Programming.”
Any frame can be prematurely aborted by an Abort sequence. Aborts are
detected if seven or more 1s occur, causing an External/Status interrupt (if
enabled) with the Break/Abort bit in RR0 set. After the Reset External/
Status interrupts command has been issued, a second interrupt occurs when
the continuous 1s condition has been cleared. This can be used to distin-
guish between the Abort and Idle line conditions.
Unlike the synchronous mode, CRC calculation in SDLC does not have an
8-bit delay because all the characters are included in CRC calculation.
When the second CRC character is loaded to the receive buffer, CRC calcu-
lation is complete.
Table 10 lists steps employed to implement a half-duplex SDLC receive
mode. The complete set of command and status bit definitions is provided
in the next section.
Typical Program Steps
Channel 2
Pointer 2
Interrupt Vector
Pointer 4
Comments
Reset SIO
Channel B only
Serial Input/Output