Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 267
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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Part Number:
Z0847006PSG
Manufacturer:
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UM008101-0601
3. To force the Z80 SIO to send CRC, the CPU issues the Reset
4. The CPU satisfies this interrupt by loading pad characters to the transmit
5. With this sequence, CRC is followed by a pad character instead of a
6. From this point on the CPU can send more pad characters or sync
Bisync CRC Generation
Setting the Transmit CRC enable bit (WR5, D0) initiates CRC accumula-
tion when the program sends the first data character to the Z80 SIO.
Although the Z80 SIO automatically transmits up to two sync characters
(18-bit sync), it is recommended to send a few more sync characters ahead
of the message (before enabling Transmit CRC) to ensure synchronization
at the receiving end.
The transmit CRC Enable bit can be changed at any time in the message to
include or exclude a particular data character from CRC accumulation. The
Transmit CRC Enable bit should be in the suitable state when the data char-
acter is loaded from the transmit data buffer to the transmit shift register. To
ensure this bit is in a suitable state, the Transmit CRC Enable bit must be
issued before sending the data character to the Z80 SIO.
Transmit Underrun/EOM Latch command (WR0) and satisfies the
interrupt with the Reset Transmit Interrupt Pending command. (This
command prevents the Z80 SIO from requesting more data.) Because
of the transmit underrun caused by this command, the Z80 SIO starts
sending CRC. The Z80 SIO also causes an External/Status interrupt
with the Transmit Underrun/EOM latch set.
buffer and issuing the Reset External/Status Interrupt command.
sync character. The Z80 SIO interrupts with a Transmit Buffer Empty
interrupt when CRC is completely sent and that the pad character is
loaded to the transmit shift register.
characters.
Z80 CPU Peripherals
Serial Input/Output
User Manual
247
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