Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 319

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Figure 123. Read Register 1
Parity Error (D4)
When parity is enabled, this bit is set for those characters whose parity does
not match the programmed sense (even/odd). The bit is latched, so when an
error occurs, the bit remains set until given the Error Reset command (WR0).
Receive Overrun Error (D5)
This bit indicates that more than three characters have been received
without a read from the CPU. Only the character that has been written over
is flagged with this error, but when this character is read, the error condition
is latched until reset by the Error Reset command. If Status Affects Vector
is enabled, the character that has been overrun interrupts with a Special
Receive Condition vector.
D7
D6
D5
D4
D3
1
0
1
0
1
0
1
0
Parity Error
Rx Overrun Error
CRC/Framing Error
End-of-Frame (SDLC)
D2
0
1
1
0
0
1
1
0
D1
0
0
0
1
1
1
1
0
D0
in Previous
I Field Bits
Byte
0
0
0
0
0
0
1
2
All Sent
*Residue Data for Eight Rx
Bits/Character Programmed
Z80 CPU Peripherals
Second Previous
I Field Bits in
Serial Input/Output
Byte
3
4
5
6
7
8
8
8
User Manual
*
299