Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 231

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
211
When CE and IORQ are active, but RD is inactive, the channel selected by
B/A is written to by the CPU with either data or control information as
specified by C/D. As mentioned previously, if IORQ and M1 are active
simultaneously, the CPU is acknowledging an interrupt and the Z80 SIO
automatically places its interrupt vector on the CPU data bus if it is the
highest priority device requesting an interrupt.
RD Read Cycle Status (input from CPU, active Low). If RD is active, a
memory or I/O read operation is in progress. RD is used with B/A, CE,
and IORQ to transfer data from the Z80 SIO to the CPU.
RESET Reset (input, active Low). A Low /RESET disables both /RESET
and transmitters, forces TxDA and TxDB marking, forces the modem
controls High and disables all interrupts. The control registers must be
rewritten after the Z80 SIO is reset and before data is transmitted or received.
IEI Interrupt Enable In (input, active High). This signal is used with IEO
to form a priority daisy-chain when there is more than one interrupt-
driven device. A High on this line indicates that no other device of higher
priority is being serviced by a CPU interrupt service routine.
IEO Interrupt Enable Out (output, active High). IEO is High only if IEI is
High and the CPU is not servicing an interrupt from this Z80 SIO. There-
fore, this signal blocks lower priority devices from interrupting while a
higher priority device is being serviced by its CPU interrupt service routine.
INT Interrupt Request (output, open-drain, active Low). When the Z80
SIO is requesting an interrupt, it pulls INT Low.
W/RDYA, W/RDYB Wait/Ready A, Wait/Ready B (outputs, open-drain
when programmed for Wait function, driven High and Low when
programmed for Ready function). These dual-purpose outputs may be
programmed as Ready lines for a DMA controller or as Wait lines that
synchronize the CPU to the Z80 SIO data rate. The reset state is open-drain.
CSTA, CSTB Clear To Send (inputs, active Low). When programmed as
Auto Enables, a Low on these inputs enables the respective transmitter. If
not programmed as Auto Enables, these inputs may be programmed as
UM008101-0601
Serial Input/Output