Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 214

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
RD* = RD • CE • C/D • IORQ
Port Input
(8 Bits)
Strobe
Ready
RD*
INT
Φ
Bidirectional Mode (Mode 2)
PIO. If already active, Ready is forced low for one and one-half Φ periods
following the leading edge of IORQ during a read of a PIO port.
Figure 8.
This mode is a combination of Mode 0 and Mode 1, using all four hand-
shake lines. Because this mode requires all four lines, it is available only on
Port A. When this mode is used on Port A, Port B must be set to the Bit
Control Mode. The same interrupt vector is returned for a Mode 3 interrupt
on Port B and an input transfer interrupt during Mode 2 operation of Port A.
Ambiguity is avoided if Port B is operated in a polled mode and the Port B
mask register is set to inhibit all bits.
Figure 9 illustrates the timing for this mode. It is almost identical to that
previously described for Mode 0 and Mode 1 with the Port A handshake
lines used for output control and the Port B lines used for input control. The
difference between the two modes is that, in Mode 2, data is allowed out
onto the bus only when the A strobe is Low. The rising edge of this strobe
can be used to latch the data to the peripheral because the data remains stable
Sample
Mode 1 (Input) Timing
Parallel Input/Output