Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 117

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
 
Stop on Match
Setting bit 2 of the base register byte to 1 causes the DMA to stop and
release the bus when a data byte matches the match byte, which is
described later. A search or transfer/search operation must be specified in
WR0 to make this bit valid when set. If this bit is 0 (no stop on match), a
status flag is still set in the status byte when a match occurs and there still
remains the option of interrupting on match (see WR4). No stop or interrupt
on match in the search class is used to obtain simultaneous transfers
without searching actions.
Match Byte
When bit 4 of the base register is set to 1, the match byte that is compared
with every data byte searched must be specified. A search operation must
be specified in WR0 to make this bit valid, as shown in the following
function.
Mask Byte
When bit 3 is set to 1, the mask byte must be subsequently specified. Bit
positions that contain 1s in the mask byte cause comparisons at those same
bit positions in the match byte (see preceding paragraph) to be ignored. For
example, if the mask byte is 00001111, only the high four bits of the match
byte is compared to the data bytes being searched.
Interrupt Enable
A 1 in bit 5 of the base register enables the DMA to generate an interrupt.
This function duplicates the ENABLE INTERRUPTS command in WR6.
UM008101-0601
Direct Memory Access