Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 137

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
interrupts and reinitialization of the status byte as well as many other func-
tions, including class and mode designation, port designation, address and
block-length designation.
Table 15 lists the order in which control bytes must be written for the
initialization or reinitialization because of program abort. Some of these
control bytes may not be relevant to a specific application. All commands
referred to are WR6 control bytes. Thirty-five control bytes occur when all
of the control bytes are written.
All control bytes written to the DMA disable the DMA, except the
ENABLE DMA command and possibly also the REINITIALIZE STATUS
BYTE command and the WR0 control byte (when changing transfer direc-
tions). The ENABLE DMA command must always be the last command
written after any communication between the CPU and DMA if the DMA
is to continue operating. Furthermore, communication with the DMA can
only occur when the CPU is bus master.
Table 15. Control Byte Order
Initialization/Reinitialization Sequence
DISABLE DMA Command
RESET Command (Multiple)
WR0 Control Bytes
WR1 Control Bytes
WR2 Control Bytes
WR3 Control Bytes
WR4 Control Bytes
WR5 Control Bytes
RESET PORT A TIMING Command
RESET PORT B TIMING Command
LOAD Command
Maximum Number of Z80 CPU
Bytes
1
6
5
2
2
3
5
1
1
1
1
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N