Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 118

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Write Register 4 Group
DMA Enable
A1 in bit 6 of the base register enables the DMA to request the bus. This
function duplicates the ENABLE DMA command in WR6 and is used as
the last control byte written to the DMA prior to allowing the DMA to
usurp the bus from the CPU. The ENABLE DMA command is often better
for this purpose.
Figure 43.
Bits 7, 1, and 0, which Figure 44 shows, select the base register byte for this
group. The group specifies the following characteristics:
Operating Mode
Bits 6 and 5 of the base register specify the operating mode as Byte, Burst,
or Continuous. For a review of these modes, see Figure 41 through
Figure 44, Table 13 and Table 15.
DMA Enable = 1
Interrupt Enable = 1
Write Register 3 Group
D7 D6 D5 D4 D3 D2 D1 D0
0
1 = Stop on Match
0
0
Mask Byte (0 = Compare)
Match Byte
Base Register Byte
Direct Memory Access