Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 112

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Source and Destination
Bit 2 indicates the source port and, by implication, the destination port, if
the operation is a sequential transfer. When bit 2 is 0, Port B is the source;
when bit 2 is 1, Port A is the source. Search-only operations have only a
source port. If the operation is a simultaneous transfer or transfer/search
(where the class is set to search-only), external hard wiring determines the
destination port.
The direction of transfer should only be changed from its current setting
after the DMA is disabled by writing some other control byte to it.
Therefore, the WR0 byte should not be the first byte written to the DMA if
changing the direction of transfer.
Port A Starting Address
If Port A is used for either source or destination, its starting address must be
programmed. Set bits 3 and 4 in the base register byte to 1 so that the next
two bytes written to the DMA are recognized as the low and high bytes,
respectively, of the Port A starting address. This address is interpreted in the
context of the entries in WR1 bits 3 through 5, which differentiate the
address as either memory or I/O, fixed or variable, and, if variable, incre-
menting or decrementing. If Port A is to be a fixed address destination port,
see the section following entitled “Fixed-Address Destination Ports.”
Direct Memory Access