Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 258

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

238
SYNCHRONOUS OPERATION
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Overview
character received is loaded into the buffer; the character preceding it is
lost. When the character that has been written over the other characters is
read, the Receive Overrun bit is set and the Special Receive. Condition
vector is returned if Status Affects Vector is enabled.
In a polled environment, the Receive Character Available bit (RR0, D0)
must be monitored so that the Z80 CPU knows when to read a character.
This bit is automatically reset when the receive buffers are read. To prevent
overwriting data in polled operations, the transmit buffer status must be
cheeked before writing to the transmitter. The Transmit Buffer Empty bit is
set to 1 whenever the transmit buffer is empty.
Before describing synchronous transmission and reception, the three types
of character synchronization, Monosync, Bisync, and External Sync,
require explanation. These modes use the x1 clock for both Transmit and
Receive operations. Data is sampled on the rising edge of the Receive
Clock input (RxC). Transmitter data transitions occur on the falling edge of
the Transmit Clock input (TxC).
The differences between Monosync, Bisync, and External Sync are in the
form in which initial character synchronization is achieved. The mode of
operation must be selected before sync characters are loaded, because the
registers are used differently in the various modes.
formats for all three of these synchronous modes.
Figure 112
Serial Input/Output
depicts the