Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 96

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
When the DMA has requested and received the bus from the CPU, other
devices on the system do not perceive the change. The CPU is idle during
this time because it cannot fetch instructions from memory.
Bus Requesting
Two conditions enable the DMA to request the bus from the CPU: an
enabling command from the CPU, and an active Ready condition, resulting
from either an active Ready line from an I/O device or a Force Ready
command by the CPU.
The DMA requests the bus by latching its BUSREQ line Low. The CPU
always responds to a bus request and it does so quickly, in no more than one
machine cycle (3 to 10 clock cycles) plus one additional clock cycle by
lowering its BUSACK line as an input to the DMA’s BAI line. Both the
DMA’s BUSREQ output and the CPU’s BUSACK output remain Low
while the DMA has the bus.
The bus is released back to the CPU when the DMA’s BUSREQ line goes
High; the CPU’s BUSACK line goes High in the next clock cycle. The
DMA releases its BUSREQ line in a variety of conditions, including:
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These conditions are explained in the “Timing” chapter. Bus requests
cannot be made while the CPU services an interrupt from the DMA. This
is prevented by the Interrupt Under Service (IUS) latch, which is
discussed later.
Completion of single-byte transfer (Byte mode
Ready line going inactive (Byte and Burst modes)
Byte match (Burst and Continuous modes) if stop-on-match is
programmed
End-of-block (all modes), if stop-on-end-of-block is programmed
Direct Memory Access