Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 291

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10. SDLC Receive Mode (Continued)
UM008101-0601
Function
Termination
Typical Program Steps
When End Of Frame Interrupt occurs, the
CPU performs
the following:
• Exits DMA Mode (disables Wait/
Ready)
• Transfers RR1 to the CPU
• Checks the CRC error bit status and
residue codes
• Updates NR count
• Issues Error Reset Command to SIO
When Abort Sequence Detected Interrupt
occurs, the CPU performs the following:
• Transfers RR0 to the CPU
• Exits DMA Mode
• Issues the Reset External Status
Interrupt Command to the SIO
• Enters the Idle Mode
When the second Abort Sequence
Interrupt occurs, the CPU performs the
following:
• Issues the Reset External Status
Interrupt Command to the SIO
Redefine Interrupt Modes, Sync Mode
and SDLC Modes, Disable Receive
Mode
Comments
Detection of End-of-frame (flag)
causes Interrupt and deactivates the
Wait/Ready function. Residue codes
indicate the bit structure of the last
two bytes of the message that were
transferred to memory under DMA.
'error Reset' is issued to clear the
special condition. Abort Sequence is
detected when seven or more 1s occur
in the data stream.
CPU is waiting for Abort Sequence to
terminate. Termination clears the
Break/Abort status bit and causes
interrupt. at this point, the program
proceeds to terminate this message.
Z80 CPU Peripherals
Serial Input/Output
User Manual
271