Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 179

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Figure 66.
The next bus request for the next byte comes after both BUSREQ and BAI
have returned High. In a Z80 environment, BAI returns High one clock
cycle after BUSREQ returns High.
Bus Release on End-of-Block.
When the DMA is programmed to stop on end-of-block in Burst or Contin-
uous modes, an end-of-block causes BUSREQ to go High (inactive) on the
same rising edge of CLK in which the DMA completes the data block
transfer (see Figure 67). The last byte in the block is transferred even if
RDY goes inactive before completion of the last byte operation.
Figure 67.
BUSREQ
BUSREQ
RDY
CLK
BAI
Active
Inactive
DMA Active
Bus Release in Byte Mode
Bus Release on End-of-Block (Burst and Continuous Modes)
Current Byte
Operation
DMA Inactive
DMA
Inactive
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N