Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 106

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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For non-Z80 environments, control bytes are provided to simulate these
actions.
Interrupt Daisy-Chains
Multiple DMAs can be chained together by their IEI and IEO lines, as
depicted in Figure 37. In the Z80 Family, the DMA’s location in the IEI/
IEO chain sets priority.
When peripherals simultaneously interrupt the Z80 CPU, the highest
priority peripheral (nearest the +5V end of the daisy-chain) is serviced. The
CPU receives the winning peripheral’s interrupt vector. The IEI/IEO chain
allows only the highest priority interrupting peripheral to place its interrupt
vector on the data bus. In non-Z80 environments that have no interrupt
vectors, the winning peripheral is determined by successively reading the
status of all peripherals.
For a device to have priority, its IEI line must be High. When a device
needs service, it prevents downstream devices from interrupting by pulling
its IEO line Low. The next device in the chain then passes this Low
condition on to other downstream devices by pulling its IEO line Low, and
so on.
Whenever an interrupt is acknowledged (Figure 32), the CPU’s interrupt
structure is disabled. It must subsequently be reenabled by an enable inter-
rupts instruction before other devices can interrupt again. This normally
takes place within the interrupt service routine. When done early in the
service routine, this permits higher priority peripherals to interrupt the CPU
while the latter is still executing that service routine. Thus, nested interrupts
Resets the Interrupt Under Service (IUS) latch in the DMA, thereby
allowing its IEO pin to go High so that lower priority devices can
interrupt.
Enables the DMA to request the bus again. This occurs only in the
Interrupt on Ready option and only when the Enable DMA control
byte is also used.
Direct Memory Access