Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 79

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Events and Actions
be independently programmed as 2, 3, or 4 clock cycles long (more if Wait
cycles are used), thereby increasing or decreasing the speed at which all
DMA signals change.
Second, the four signals in each port (I/O Request, Memory Request, Read,
and Write) can each have its active trailing edge terminated one-half clock
cycle early. This adds a further flexibility by allowing functions such as
shorter-than-normal Read or Write signals to go inactive before data starts
to change. Figure 24 illustrates the general capability, which is described
later in “Timing” on page 151”
Figure 24.
Table 10 gives an overview of the events that can cause specific actions by
the DMA, depending on how it is programmed. The events are conditions
in the DMA’s internal registers, signals from the I/O device, or instructions
on the data bus for which the DMA watches.
CLK
T
Variable Cycle Length
1
3-Cycle
4-Cycle
2-Cycle
T
2
T
3
T
4
Early Ending
for Control Signals
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N