Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 64

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Classes of Operation
The Z80 DMA has three basic classes of operation, and two of the classes
are each broken into subclasses as follows:
•
•
•
Figure 18 illustrates these classes. The two subclasses of transfers are illus-
trated at the top; the search-only class is depicted in the middle, and the two
subclasses of transfer-while-searching are featured at the bottom. In all
cases, the DMA assumes full control of the system address, data, and
control buses while transferring or searching a given byte. The DMA ports
are the source and destination of data; a port is used here to mean either
memory or an I/O device.
In sequential transfers, which are sometimes called flow-through transfers,
each byte transfer includes a read cycle followed by a write cycle. The DMA
reads the byte via the data bus to an internal register and sustains the byte on
the data bus into the subsequent write cycle. In a Z80 CPU environment, as
well as in certain other CPU environments, sequential DMA transfers can be
implemented with no external logic between the DMA and the CPU.
In simultaneous transfers, which are sometimes called flyby transfers,
each byte is simultaneously read from the source into the DMA and
written from the source directly to the destination in a single machine
cycle. These transfers, therefore, occur at twice the rate of sequential
transfers, but they require at least one external logic package to cause the
proper signals to appear simultaneously on the control bus (see “The
actual number of bytes transferred is one more than specified by the block
Transfers of data between any two DMA ports:
–
–
Searches for a particular bit pattern within a byte at a single DMA port
Combined transfers and searches between any two DMA ports:
–
–
Sequential transfers (flow-through)
Simultaneous transfers (flyby)
Sequential transfer/search
Simultaneous transfer/search
Direct Memory Access