Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 313

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z80 CPU Peripherals
User Manual
293
Interrupt Pending (D1)
Any interrupting condition in the Z80 SIO causes this bit to set; however, it
is readable only in Channel A. This bit is primarily used in applications not
having vectored interrupts available. During the interrupt service routine in
these applications, this bit indicates if any interrupt conditions are present
in the Z80 SIO. This eliminates the need for analyzing all the bits of RR0 in
both Channels A and B. Bit D1 is reset when all the interrupting conditions
are satisfied. This bit is always 0 in Channel B.
Transmit Buffer Empty (D2)
This bit is set whenever the transmit buffer becomes empty, except when a
CRC character is being sent in a synchronous or SDLC mode. The bit is
reset when a character is loaded into the transmit buffer. This bit is in the set
condition after a reset.
Data Carrier Detect (D3)
The DCD bit indicates the state of the DCD input at the time of the last
change of any of the five External/Status bits (DCD, CTS, Sync/Hunt,
Break/ Abort, or Transmit Underrun/EOM). Any transition of the DCD
input causes the DCD bit to latch and causes an External/Status interrupt.
To read the current state of the DCD bit, this bit must be read immediately
following a Reset External/Status Interrupt command.
Sync/Hunt (D4)
Because this bit is controlled differently in the Asynchronous,
Synchronous, and SDLC modes, its operation is somewhat more complex
than that of the other bits and therefore requires more explanation.
In asynchronous modes, the operation of this bit is similar to the DCD
status bit, except that Sync/Hunt shows the state of the SYNC input. Any
High-to-Low transition on the SYNC pin sets this bit and causes an
External/Status interrupt (if enabled). The Reset External/Status Interrupt
command is issued to clear the interrupt. A Low-to-High transition clears
UM008101-0601
Serial Input/Output