Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 133

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
  
Read Status Byte
This command causes the next CPU read of the DMA to access the status
byte, which is the first read register.
Initiate Read Sequence
This command initializes access to a repeatable series of reads that follow
the sequence defined in the read mask.
These commands are described in the immediately preceding pages, and
Figure 46 illustrates the read mask. As mentioned in the description of
these commands, the reading of registers do not need to be contiguous in
time with these write commands or with other CPU read instructions
accessing registers in the same read sequence.
Two other commands are also related to the read registers:
Reinitialize Status Byte
This command reinitializes bits 4 and 5 of the status byte to 1s.
Read Mask Follows
This command allows the read mask to be programme. Figure 47 illustrates
more clearly the group of the seven read registers in relation to the write
registers. The read registers include:
Status Byte (RR0)
The status byte can be read independently from the other read registers and
two of its bits can be reinitialized to identify end-of-block and match bytes.
The bits in the status byte are defined as follows:
UM008101-0601
Direct Memory Access