Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 197

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
Interface
CPU
PIO Control
Data Bus
Lines
8
6
The 2-bit mode control register is loaded by the CPU to select the desired
operating mode (byte output, byte input, byte bidirectional bus, or bit
control mode). All data transfer between the peripheral device and the
CPU is achieved through the data input and data output registers. Data
may be written into the output register by the CPU or read back to the
CPU from the input register at any time. The handshake lines associated
with each port are used to control the data transfer between the PIO and
the peripheral device.
Figure 1.
PIO Block Diagram
Interrupt Control Lines
Interrupt Control
Internal Control
Internal Bus
Logic
+5V GND Φ
3
Port
I/O
Port
I/O
B
A
8
8
<   % 2 7 2 G T K R J G T C N U
Data or Control
Data or Control
Handshake
Handshake
Parallel Input/Output
7 U G T / C P W C N
Peripheral
Interface