Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 170

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
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7 U G T / C P W C N
Figure 59.
To write to the DMA control bites, the following conditions must be met:
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Reading Status Bytes
Figure 60 illustrates the timing needed for the CPU to read the DMA’s read
registers, RR6 through RR0, while the CPU is bus master. To read a regis-
ter, this condition must be met: The CE, IORQ, and RD lines must be
active and stabilized over two rising edges of the clock.
Status data becomes available on the data bus at the time of the second
clock rising edge, which remains on the bus for as long as both the CE,
IORQ, and RD lines remain active.
The DMA’s CE line must be Low (normally done by decoding the
lower byte of the address bus).
The IORQ and WR lines must be Low at this time.
The control byte must be placed on the data bus so that it is stabilized
at a rising clock edge, which occurs one clock period after the CE,
IORQ, and WR lines have stabilized.
D7–D0
IORQ
CLK
WR
CE
CPU-to-DMA Write Cycle Requirements
Direct Memory Access