Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 167

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERFORMANCE LIMITATIONS
UM008101-0601
Bus Contention
Using the Direct Memory Access (DMA) as bus master can negatively
effect CPU activity by preventing the CPU from fetching and executing
instructions. This method of bringing the CPU to a halt creates problems,
including:
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The CPU’s time-critical functions are affected by which operating mode
the DMA is using. These modes are Byte, Burst, and Continuous.
Byte Mode
When bus contention occurs, using Byte Mode allows interleaving of
CPU functions and DMA functions for each byte of data transferred. The
disadvantage to using this mode is slower transfer speed.
Burst Mode
Burst mode is useful when transferring data in short segments over a
longer period of time. This mode has the advantage of using the bus only
when needed. During those times, transfer speeds are maximized.
However, this mode may not be suitable for extended bursts of data (long
periods when the Ready line is active). Burst mode allows the DMA to
release the bus back to the CPU before other CPU-dependent functions
are compromised.
No interrupt servicing (including nonmaskable CPU interrupts)
No refresh of dynamic memory (if performed by the CPU)
No polling
<   % 2 7 2 G T K R J G T C N U
Direct Memory Access
7 U G T / C P W C N